One common isolation technique for electrically isolating transistors is based on trench isolation. The trench isolation process is generally more suitable for semiconductor chips having high packing density, as compared to local oxidation (LOCOS) processing. A trench region is formed in conventional semiconductor substrates (e.g. Si) with a depth deep enough for isolating the devices or different wells. In general, trenches are etched using a patterned hard mask material (e.g. silicon nitride) over a pad oxide for masking the active area. A thin liner oxide is generally thermally grown and the trenches are then refilled with a deposited dielectric material, such as oxide deposited using a high-density plasma chemical vapor deposition (HDP-CVD) process.
As used herein, the term “trench isolation” applies for both conventional (e.g. bulk Si) substrates as well as silicon on insulator (SOI) substrates. Applied to conventional substrates, as used herein trench isolation includes deep trench isolation which is typically 1-5 μm deep, and shallow trench isolation which is typically <1 μm deep, such as 0.3 to 0.7 μm deep. Applied to SOI substrates, as used herein, trench isolation includes the isolation regions between the active area islands. In the case of thin-film SOI, the trench isolation regions like in the conventional substrate case are generally filled with a deposited dielectric, but are typically shallower than their conventional substrate counterparts, being generally <0.5 μm deep, such as 0.01 to 0.3 μm deep.
Typically, after the trench isolation process is completed, the pad oxide (if present) is removed and a gate oxide is thermally grown. Sometimes a sacrificial (dummy) gate oxide is grown and stripped prior to the final gate oxide growth.
As known in the art, thermally grown gate oxide thinning occurs at the trench isolation/active area edges (or corners) when the gate oxide thickness is at least several hundred Angstroms. Such thinning results from the reduced diffusion controlled (parabolic) oxidation rate at the mechanically stressed relatively sharp trench isolation edge relative to gate oxide grown in the active area away from the trench isolation edge. Although steam oxidation, higher temperature, and high pressure oxidation can prevent or at least reduce thinning at the trench isolation edge if target thickness is relatively small by extending the linear oxidation regime, such as up to about 25 to 200 Angstroms, thicker gate oxides needed for higher voltage transistors, such as from 300 to 5,000 Angstroms (e.g. for high voltage transistors 1,000 to 5,000 Angstroms for max Vg of 36 V to 200 V), result in significant thinning at the trench isolation edge which can result in yield loss or reliability problems associated with gate oxide failure. Typically, the gate oxide thickness for thicker gate oxides at the trench isolation edge is ≦75% of the gate oxide thickness over the active area away from the trench isolation edge. Accordingly, it is desirable to provide methods for fabricating an IC in which a relatively thick gate oxide, such as 300 to 5,000 Angstroms, can be grown with reduced or eliminated gate oxide thinning relative to the gate oxide thickness grown on the active area away from the trench isolation edge.